Zilog Z08470 User Manual

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Z80 CPU PeripheralsUser ManualUM008101-0601 List of FiguresxDirect Memory Access (continued)Figure24. VariableCycleLength...

UM008101-0601 Direct Memory AccessFigure 32. Z80 Interrupt SequenceInterrupt VectorsThe Z80 CPU interrupt acknowledge cycle causes the DMA to put its

UM008101-0601 Direct Memory AccessCPU to a temporary register. It normally identifies the interrupting deviceand it can also identify the cause of the

UM008101-0601 Direct Memory AccessFigure 33. Interrupt Service RoutineInterrupt LatchesTwo primary latches are associated with the interrupt structure

UM008101-0601 Direct Memory Access– Prevents interrupts from lower priority devices in an interruptdaisy-chain– Prevents further bus requests by this

UM008101-0601 Direct Memory AccessInterrupt On ReadyNormally, when the DMA has been enabled by the CPU to request the buswhile the I/O device’s Ready

UM008101-0601 Direct Memory Access•Reset and disable DMA interrupts– Enable DMA interrupts– Disable DMA interrupts•Load new starting addresses and blo

UM008101-0601 Direct Memory Access•Resets the Interrupt Under Service (IUS) latch in the DMA, therebyallowing its IEO pin to go High so that lower pri

UM008101-0601 Direct Memory Accessare allowed in which the higher priority peripheral suspends the executionof the lower priority peripheral’s service

UM008101-0601 Direct Memory AccessFigure 38. Polling for a Service Request BitPROGRAMMINGOverviewThe DMA must be programmed before use. Its control re

UM008101-0601 Direct Memory Accesschapter. It is not possible for the DMA to program itself by directingtransfers of control bytes from memory to its

Z80 CPU PeripheralsUser ManualList of Figures UM008101-0601xiDirect Memory Access (continued)Figure50. CE/WAITMultiplexer ...1

UM008101-0601 Direct Memory AccessWrite RegistersControl bytes must be written to all relevant registers in the DMA at power-up initialization. This s

UM008101-0601 Direct Memory AccessFigure 39. Write-Register Pointing MethodsWrite Register 0 GroupThe WR0 base register byte is identified by a 0 in b

UM008101-0601 Direct Memory AccessSource and DestinationBit 2 indicates the source port and, by implication, the destination port, ifthe operation is

UM008101-0601 Direct Memory AccessFigure 40. Write Register 0 GroupBlock LengthAll operations must have a declared block length because the default va

UM008101-0601 Direct Memory AccessWrite Register 1 GroupBits 7, 2, 1, and 0, as Figure 41 illustrates, select the base register byte forthis group. Th

UM008101-0601 Direct Memory AccessIn addition, bits 7, 6, 3, and 2 of the variable-timing byte allow terminationof various lines 1/2 cycle earlier tha

UM008101-0601 Direct Memory AccessWrite Register 2 GroupBits 7, 2, 1, and 0, depicted in Figure 42, specify the base register byte forthis group. The

UM008101-0601 Direct Memory AccessStop on MatchSetting bit 2 of the base register byte to 1 causes the DMA to stop andrelease the bus when a data byte

UM008101-0601 Direct Memory AccessDMA EnableA1 in bit 6 of the base register enables the DMA to request the bus. Thisfunction duplicates the ENABLE DM

UM008101-0601 Direct Memory AccessStarting Address (Port B)The starting address for Port B in the next two bytes may be specified bysetting bits 2 and

Z80 CPU PeripheralsUser ManualUM008101-0601 List of FiguresxiiDirect Memory Access (continued)Figure74. WAITLineSamplinginVariable-CycleTiming ...

UM008101-0601 Direct Memory AccessInterrupt VectorBit 4 of the interrupt control byte allows the interrupt vector to be entered.In addition, when bit

UM008101-0601 Direct Memory AccessFigure 44. Write Register 4 GroupWrite Register 5 GroupBits 7, 6, 2, 1, and 0, illustrated in Figure 45, specify the

UM008101-0601 Direct Memory AccessEnd-of-Block ActionBit 5 specifies either a stop (bus release) or an auto repeat at the end of theblocklengthprogram

UM008101-0601 Direct Memory AccessFigure 45. Write Register 5 GroupWrite Register 6 GroupThe base register byte for this group has bits 7, 1, and 0 se

UM008101-0601 Direct Memory Access•Reinitialize Ports A and B to standard Z80 cycle timing (see WR1and WR2)At power-up, one reset command is sent to t

UM008101-0601 Direct Memory Accesscates that it is never loaded. This special situation is discussed in a latersection entitled “Fixed-Address Destina

UM008101-0601 Direct Memory Accessthe routine is being executed. Near the end of the routine, the CPU writesan ENABLE INTERRUPTS command to the DIVA,

UM008101-0601 Direct Memory AccessEnable Interrupts (AB)See the preceding description of DISABLE INTERRUPTS. A Z80 CPUenvironment uses this command at

UM008101-0601 Direct Memory Accessend of the service routine, the CPU writes a RESET AND DISABLEINTERRUPTS command, then an ENABLE INTERRUPTS command,

UM008101-0601 Direct Memory Access6. •7. •8. •RETI instructionRead Status Byte (BF)This command causes the next CPU read of the DMA to access the stat

Z80 CPU PeripheralsUser ManualList of Figures UM008101-0601xiiiParallel Input/Output (continued)Figure98. ExampleofI/OInterface...

UM008101-0601 Direct Memory Accessthe DMA, reinitialization of the status bits may remove the condition thatstopped the DMA and the DMA might immediat

UM008101-0601 Direct Memory AccessInitiate Read Sequence (A7)This command initiates the read-sequence pointer command, allowing thenext CPU read instr

UM008101-0601 Direct Memory AccessEnable DMA (87)This command allows the DMA to request the system bus and proceed withits operation if all other func

UM008101-0601 Direct Memory AccessRead Status ByteThis command causes the next CPU read of the DMA to access the statusbyte, which is the first read r

UM008101-0601 Direct Memory AccessBit 0 Indicates whether the DMA has requested the bus after the fastLOAD command. 1 indicates yes, 0 indicates no.Bi

UM008101-0601 Direct Memory AccessFigure 47. Read Register 0 through Read Register 6Byte Counter (RR1, RR2)This 16-bit counter is cleared to 0 by the

UM008101-0601 Direct Memory AccessTable 11 and Table 12 illustrate how the pipelining of data affects thenumber of bytes transferred or searched in th

UM008101-0601 Direct Memory Accessinterrupts and reinitialization of the status byte as well as many other func-tions, including class and mode design

UM008101-0601 Direct Memory AccessPort DesignationEither Port A or Port B can be selected as the source or destination, (illus-trated in Figure 19) be

UM008101-0601 Direct Memory AccessAddress LoadingWrite starting addresses to the starting-address registers for each port usingWR0 (Port A) and WR4 (P

Z80 CPU PeripheralsUser ManualUM008101-0601 List of FiguresxivSerial Input/Output (continued)Figure 124. Read Register 2 (Channel B Only) ...

UM008101-0601 Direct Memory Access•••7. Enable DMA with theENABLE DMA command.InterruptsThe interrupt vector (WR4) must be written before interrupts u

UM008101-0601 Direct Memory Access5. ENABLE AFTER RETI command6.ENABLE DMA command•••7.RETI instructionInterrupts at end-of-block, for example, might

UM008101-0601 Direct Memory Accessprocessed until the bus is released). Second, to enable the DMA, theENABLE AFTER RETI command must be used in the se

UM008101-0601 Direct Memory AccessEnd-of-BlockAfter a stop or stop and interrupt on end-of-block (WR4 or WR5), where itis necessary to perform additio

UM008101-0601 Direct Memory AccessVariable TimingThe timing on the RD,WR,MREQ,andIORQlines can be varied indepen-dently for either port by programming

UM008101-0601 Direct Memory Accesscompleted before the next READ STATUS BYTE or INITIATE READSEQUENCEcommand.Table 16 illustrates a program to transfe

UM008101-0601 Direct Memory AccessWR4 sets mode toBurst and sets DMAto expect Port Baddress11 0 0NoInterruptControlByteFollows0NoUpperAddress1Port BLo

UM008101-0601 Direct Memory AccessNote: The actual number of bytes transferred is one more than specified by the block length.* These entries are nece

UM008101-0601 Direct Memory Accessup. A complementary-transistor driver for Z80/Z8000 systems is depictedin Figure 48.Chip Selection and EnablingZ80 p

UM008101-0601 Direct Memory AccessFigure 49c depicts a one-of-eight TTL decoder which provides chip enablesignals for eight different peripheral devic

Z80 CPU PeripheralsUser ManualList of Tables UM008101-0601xvList of TablesCounter/Timer ChannelsTable1. ChannelValues ...

UM008101-0601 Direct Memory AccessFigure 49. Chip Enable Decoding with Z80 CPUUse of WAIT InputWhen the DMA is bus master, the CE/WAIT pin functions a

UM008101-0601 Direct Memory AccessCPU has relinquished the bus. Therefore, if this DMA is bus master, itsamples the WAIT signal for these requests. A

UM008101-0601 Direct Memory AccessFigure 50. CE/WAIT MultiplexerFigure 51. Simultaneous Transfer MultiplexerI1 I0SEL1/474LS157YDMACE/WAITBUSACKCE (Fro

UM008101-0601 Direct Memory AccessFigure 52. Simultaneous TransferDMAIORQRD WR BUSACKBAI RD IORQMRDMWRHIGHRD WRMEMORYI/ODMAI/ODECODERIOCEIOWRIORDAddre

UM008101-0601 Direct Memory AccessFigure 53. Delaying the Leading Edge of MWRBus BufferingMicrocomputer systems using DMA often include large memories

UM008101-0601 Direct Memory Access(floated) in a manner similar to the CPU and DMA address pins. Forexample, in a system with one CPU and one DMA, the

UM008101-0601 Direct Memory Accesssignals. To maximize current, the system’s BUSREQ pull-up resistor can beas low as 1.8 Kohms.TTL buffers and drive c

UM008101-0601 Direct Memory AccessFigure 54. Data Bus Buffer Control ExampleZ80 DMA and Z80 SIO ExampleA common DMA application is performing data tra

UM008101-0601 Direct Memory AccessThe event sequences for SIO-DMA transfers are described in Table 17 andTable 18.Table 17. Receive Event SequenceEven

UM008101-0601 Direct Memory AccessIn an interrupt-driven CPU transfer scheme, the SIO must interrupt the CPUwhenever it has received a character or ne

Z80 CPU PeripheralsUser ManualUM008101-0601 List of TablesxviParallel Input/OutputTable19. PIOModeSelection... 189Serial Inp

UM008101-0601 Direct Memory Accessrepresent the fractional reductions in CPU throughput per Kbaud trans-ferred.The DMA has a shorter and more predicta

UM008101-0601 Direct Memory AccessFigure 55. DMA-SIO EnvironmentUsing The Z80 DMA With Other ProcessorsThe Z80 DMA offers great versatility and is a p

UM008101-0601 Direct Memory Accessthe Z80 bus, to function. These functions are described in the followingsections, and design solutions are offered:•

UM008101-0601 Direct Memory AccessBus CharacteristicsSimilar to the Z80, the 8080 and 8085 have 8-bit data paths and 16-bitaddresses. The DMA is match

UM008101-0601 Direct Memory AccessFigure 56. Connecting DMA to Demultiplexed Address/Data BusesMany processors encode their control signals, as does t

UM008101-0601 Direct Memory AccessNon-Z80 interrupt environments do not use the IEI and IEO signals, andoften they use separate interrupt controllers

UM008101-0601 Direct Memory AccessFigure 57. Z8000/Z80 Peripheral Interface+5VCLRCLKLS74DQPREQLS32LS10LS10LS32LS04Y0Y1Y2Y3Y4Y5RETIG1G2AG2BCBALS138+5VI

UM008101-0601 Direct Memory AccessPERFORMANCE LIMITATIONSBus ContentionUsing the Direct Memory Access (DMA) as bus master can negativelyeffect CPU act

UM008101-0601 Direct Memory AccessContinuous ModeContinuous Mode monopolizes the bus until the end-of-block or bytematch is reached, regardless of the

UM008101-0601 Direct Memory AccessSystem throughput is decreased for applications requiring frequent DMAreprogramming or extensive interrupt service o

Z80 CPU PeripheralsUser ManualList of Tables UM008101-0601xviiSerial Input/Output (continued)Table43. SyncModes...286

UM008101-0601 Direct Memory AccessFigure 59. CPU-to-DMA Write Cycle RequirementsTo write to the DMA control bites, the following conditions must be me

UM008101-0601 Direct Memory AccessFigure 60. CPU-to-DMA Read Cycle RequirementsThe DMA As Bus MasterSequential TransfersIn sequential transfer and tra

UM008101-0601 Direct Memory AccessSimultaneous TransfersThe timing for simultaneous transfers and simultaneous transfer/searches isthe same. The DMA i

UM008101-0601 Direct Memory AccessFigure 61.Sequential Memory-to-I/O Transfer, Standard Timing (Searching is Optional)CE/WAITD7–D0MemoryDrive DMADMA D

UM008101-0601 Direct Memory AccessFigure 62. Sequential I/O-to-Memory Transfer, Standard Timing(Searching is Optional)CE/WAITI/O DrivesMemoryDMA Drive

UM008101-0601 Direct Memory AccessFigure 63. Simultaneous Memory-to-I/O Transfer (Burst and ContinuousMode)CE/WAITA15–A0CLKT1T2T3D7–D0IOWRMEMRDCycle 1

UM008101-0601 Direct Memory AccessFigure 64. Simultaneous Memory-to-I/O Transfer (Byte Mode)Figure 63 illustrates the timing for simultaneous transfer

UM008101-0601 Direct Memory Accessinactive, are caused by the activity on the BUSREQ and BAI lines, which isexplained later.Search-OnlyThe standard ti

UM008101-0601 Direct Memory AccessFigure 65. Bus Request and Acceptance TimingContinuous mode is the only instance when a pulse on RDY allows theDMA t

UM008101-0601 Direct Memory AccessFigure 66. Bus Release in Byte ModeThe next bus request for the next byte comes after both BUSREQ and BAIhave return

Z80 CPU PeripheralsUser ManualUM008101-0601 List of Tablesxviii

UM008101-0601 Direct Memory AccessBus Release on MatchWhen the DMA is programmed to stop (release the bus) on match in Burstor Continuous modes, a mat

UM008101-0601 Direct Memory Accesssearch (Figure 69). The action on BUSREQ is thus somewhat delayed fromaction on the RDY line. The DMA always complet

UM008101-0601 Direct Memory AccessFigure 70. RDY Line in Byte ModeA15–A0D7–D0RDMREQBUSREQBAIRDYActive

UM008101-0601 Direct Memory AccessFigure 71. RDY Line in Burst ModeA15–A0D7–D0RDMREQBUSREQBAIRDY

UM008101-0601 Direct Memory AccessFigure 72. RDY Line in Continuous ModeVariable Cycle and Edge TimingThe Z80 DMA’s operation-cycle length, without Wa

UM008101-0601 Direct Memory AccessFigure 73. Variable-Cycle and Edge TimingIn the Variable-Cycle mode, unlike default tuning, IORQ comes active one-ha

UM008101-0601 Direct Memory Accessand any functions created from it by external logic in simultaneous transferoperations (such as IOWR and IORD), rema

UM008101-0601 Direct Memory AccessInterrupt on RDY (interrupt before requesting the bus) does not directlyaffect the BUSREQ line. Instead, the interru

UM008101-0601 Direct Memory AccessFigure 75. Interrupt AcknowledgeA7–A0RDWAITCLOCKININTDATABUSM1IORQMREQPCLast MCycleof InstructionT1Last T StateM1Ref

UM008101-0601 Direct Memory AccessREGISTER BIT FUNCTIONSWrite Register Bit FunctionsFigure 76. Write Register 0 GroupFigure 77. Write Register 1 Group

UM008101-0601 Counter/Timer ChannelsCounter/Timer ChannelsCTC FEATURES•Four independently programmable counter/timer channels (CTC),each with a readab

UM008101-0601 Direct Memory AccessFigure 78. Write Register 2 GroupFigure 79. Write Register 3 GroupD7 D6 D5 D4 D3 D2 D1 D0Base Register Byte00011101=

UM008101-0601 Direct Memory AccessFigure 80. Write Register 4 GroupD7 D6 D5 D4 D3 D2 D1 D0Base Register Byte0000= Interrupt on End-of-Block= Interrupt

UM008101-0601 Direct Memory AccessFigure 81. Write Register 5 GroupFigure 82. Write Register 6 GroupD7 D6 D5 D4 D3 D2 D1 D0Base Register Byte0= Ready

UM008101-0601 Direct Memory AccessRead Register Bit FunctionsFigure 83. Read Register 0 through 6 Bit FunctionsD7 D6 D5 D4 D3 D2 D1 D0Status ByteXX1 =

UM008101-0601 Direct Memory Access

UM008101-0601 Parallel Input/OutputParallel Input/OutputOVERVIEWThe Z80 Parallel Input/Output (PIO) Circuit is a programmable, two-portdevice that pro

UM008101-0601 Parallel Input/Output•Four modes of port operation with interrupt-controlled handshake:– Byte Output– Byte Input– Byte Bidirectional Bus

UM008101-0601 Parallel Input/OutputThe 2-bit mode control register is loaded by the CPU to select the desiredoperating mode (byte output, byte input,

UM008101-0601 Parallel Input/OutputFigure 2. Port I/O Block DiagramUse the 8-bit mask register and the 8-bit input/output select register onlyin the B

UM008101-0601 Parallel Input/OutputThe interrupt control logic section handles all CPU interrupt protocol fornested priority interrupt structures. The

Z80 CPU PeripheralsUser ManualUM008101-0601 DisclaimeriiThis publication is subject to replacement by a later edition. To determine whether a lateredi

UM008101-0601 Counter/Timer Channelsmicrocomputer system requirements for event counting, interrupt andinterval timing, and general clock rate generat

UM008101-0601 Parallel Input/OutputPIN DESCRIPTIONFigure 3 illustrates a diagram of the Z80 PIO pin configuration. Thissection describes the function

UM008101-0601 Parallel Input/OutputΦSystem Clock (input). The Z80 PIO uses the standard Z80 system clock tosynchronize certain signals internally. Thi

UM008101-0601 Parallel Input/OutputIEIInterrupt Enable In (input, active High). This signal is used to form apriority interrupt daisy-chain when more

UM008101-0601 Parallel Input/Output3. Bidirectional mode: When this signal is active, data from the Port Aoutput register is gated onto Port A bidirec

UM008101-0601 Parallel Input/OutputBRDYRegister B Ready (output, active High). The meaning of this signal issimilartothatofAReadywiththefollowingexcep

UM008101-0601 Parallel Input/OutputFigure 4. 44-Pin PLCC Pin Assignments

UM008101-0601 Parallel Input/OutputFigure 5. 44-Pin QFP Pin Assignments3433N/CCS1CLK/TRG3CLK/TRG2N/CN/CCLK/TRG1CLK/TRG0N/C+5VN/CIEOIORQN/CZC/TO2ZC/TO1

UM008101-0601 Parallel Input/OutputFigure 6. 40-Pin DIP Pin AssignmentsPROGRAMMING THE PIOResetThe Z80 PIO automatically enters a reset state when pow

UM008101-0601 Parallel Input/OutputIn addition to the automatic power-on reset, the PIO can be reset byapplying an M1 signal without the presence of a

UM008101-0601 Parallel Input/OutputSelectingAnOperatingModePIO Port A allows operation in four modes: Mode 0 (output mode), Mode 1(input mode), Mode 2

UM008101-0601 Counter/Timer Channelspriority. The CPU bus interface logic allows the CTC device to interfacedirectly to the CPU with no other external

UM008101-0601 Parallel Input/Outputdata is available. This signal remains High until a strobe is received fromthe peripheral. The rising edge of the s

UM008101-0601 Parallel Input/OutputCPU is composed of input data, which comes from port data bus linesassigned as inputs, and port output register dat

UM008101-0601 Parallel Input/OutputOnly port lines whose mask bit is zero are monitored for generating aninterrupt. When IORQ is high, the forced stat

UM008101-0601 Parallel Input/OutputIf the PIO is not in a reset state, the output register may be loaded beforeMode 0 is selected. This allows the por

UM008101-0601 Parallel Input/OutputPIO. If already active, Ready is forced low for one and one-half Φ periodsfollowing the leading edge of IORQ during

UM008101-0601 Parallel Input/Outputafter this edge has risen. The input portion of Mode 2 operates identically toMode 1. Notice that both Port A and P

UM008101-0601 Parallel Input/OutputWhen reading the PIO, the data returned to the CPU is composed of outputregister data from port data lines assigned

UM008101-0601 Parallel Input/OutputINTERRUPT SERVICINGAfter an interrupt is requested by the PIO, the CPU sends out an interruptacknowledge (M1 and IO

UM008101-0601 Parallel Input/OutputFigure 11. Interrupt Acknowledge TimingFigure 12. Return from Interrupt CycleΦM1IORQINTIORQ and M1indicate Interrup

UM008101-0601 Parallel Input/OutputFigure 13. Daisy-Chain Interrupt ServicingAPPLICATIONSExtending The Interrupt Daisy-chainWithout external logic, a

UM008101-0601 Counter/Timer ChannelsIn Channel Control Register and LogicThe Channel Control register (8-bit) and Logic is written to by the CPU tosel

UM008101-0601 Parallel Input/OutputIf more than four PIO devices must be accommodated, a look-ahead struc-ture may be used as shown in Figure 14. With

UM008101-0601 Parallel Input/OutputInterrupts are then enabled by the rising edge of the first M1 after the inter-rupt mode word is set unless that fi

UM008101-0601 Parallel Input/OutputControl InterfaceA typical control mode application is illustrated in Figure 16. In thisexample, an industrial proc

UM008101-0601 Parallel Input/OutputIf a sensor puts a High level on lines A5, A3, or A0, an interrupt request isgenerated. The mask word may select an

UM008101-0601 Parallel Input/OutputFigure 16. Control Mode ApplicationZ80 CPUZ80 PIOIndustrialProcessingSystemB/A C/D CEA15–A0D7–D0Spec. TestTurn on P

UM008101-0601 Parallel Input/OutputPROGRAMMING SUMMARYOverviewThis section discusses the Load Interrupt Vector, Set Mode, Set Interruptcontrol registe

UM008101-0601 Parallel Input/OutputSet Interrupt ControlIf the mask follows bit is high, the next control word written to the portmust be the mask:In

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output207Serial Input/OutputOVERVIEWThe Z80 Serial Input/Output (SIO) is a dual-channel multi

UM008101-0601 Serial Input/Output208•TTL-Compatible Inputs and Outputs•Two Independent Full-Duplex Channels•Data Rates in Synchronous or Isosynchronou

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output209•CRC generation and checking•Separate Modem Control Inputs and Outputs for Both Chan

UM008101-0601 Counter/Timer ChannelsThe PrescalerThe prescaler is an 8-bit device that is used in the TIMER mode only. Theprescaler is programmed by t

UM008101-0601 Serial Input/Output210PIN DESCRIPTIONPin FunctionsD7-D0 System Data Bus (bidirectional, tristate). The system data bustransfers data and

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output211When CE and IORQ are active, but RD is inactive, the channel selected byB/A is writt

UM008101-0601 Serial Input/Output212general-purpose inputs. Both inputs are Schmitt-trigger buffered toaccommodate slow-risetime inputs. The Z80 SIO d

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output213they are inputs similar to CTS and DCD. In this mode, the transitions onthese lines

UM008101-0601 Serial Input/Output214Figure 101. Z80 SIO/0 FunctionsZ80 SIO/04039383736353433323130292827262524232221D0D2D6D4IORQCEB/AC/DRDGNDW/RDYBSYN

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output215Figure 102. Z80 SIO/0 Pin AssignmentsZ80 – SIO/0CH-ARxDARxCATxDATxCASYNCAW/RDYARTSAC

UM008101-0601 Serial Input/Output216Figure 103. Z80 SIO/1 Pin FunctionsZ80 SIO/14039383736353433323130292827262524232221D0D2D6D4IORQCEB/AC/DRDGNDW/RDY

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output217Figure 104. Z80 SIO/1 Pin AssignmentsZ80 – SIO/1CH-ARxDARxCATxDATxCASYNCAW/RDYARTSAC

UM008101-0601 Serial Input/Output218Figure 105. Z80 SIO/2 Pin FunctionsZ80 SIO/24039383736353433323130292827262524232221D0D2D6D4IORQB/AC/DRDGNDW/RDYBR

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output219Figure 106. Z80 SIO/2 Pin AssignmentsZ80 – SIO/2CH-ARxDARxCATxDATxCASYNCAW/RDYARTSAC

UM008101-0601 Counter/Timer Channelsthe down-counter counts to zero, the down-counter is automaticallyreloaded with the contents of the Time Constant

UM008101-0601 Serial Input/Output220Figure 107. Z80 SIO/3 Pin Assignments3433IEIIEOM1+5VW/RDYAN/CSYNCARxDARxCATxCATxDACEB/AC/DRDGNDN/CW/RDYBSYNCBRxDBR

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output221Figure 108. Z80 SIO/4 Pin AssignmentsIEIIEOM1+5VW/RDYASYNCARxDARxCATxCATxDAB/AC/DRDG

UM008101-0601 Serial Input/Output222ARCHITECTUREOverviewThe device internal structure includes a Z80 CPU interface, internal controland interrupt logi

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output223Data PathThe transmit and receive data path for each channel is depicted inFigure 10

UM008101-0601 Serial Input/Output224entered in the 3-bit buffer if the data has a character length of seven or eightbits, or is entered in the 8-bit r

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output225during which the Z80 SIO tries to match the assembled character in thereceive shift

UM008101-0601 Serial Input/Output226Figure 109. Transmit and Receive Data PathFunctional DescriptionThe functional capabilities of the Z80 SIO are des

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output227busses, as well as being a part of the Z80 interrupt structure. As a peripheralto ot

UM008101-0601 Serial Input/Output228routine in the memory. To service operations in both channels and to elimi-nate the necessity of writing a status

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output229interrupt is also caused by a Transmit Underrun condition or by the detec-tion of a

UM008101-0601 Counter/Timer ChannelsInterrupt Control LogicThe Interrupt Control Logic insures that the CTC acts in accordance withZ80 system interrup

UM008101-0601 Serial Input/Output230Figure 110. Interrupt StructureASYNCHRONOUS OPERATIONOverviewTo receive or transmit data in the Asynchronous mode,

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output231registers by the system program. WR4 parameters must be issued beforeWR1, WR3, and W

UM008101-0601 Serial Input/Output232Asynchronous TransmitThe Transmit Data output (TxD) is held marking (High) when the trans-mitter has no data to se

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output233WR5 DTR 00 = Tx 5 Bits (or less)/Char10 = Tx 6 Bits/Char01 = Tx 7 Bits/Char11=Tx8Bit

UM008101-0601 Serial Input/Output234WR5 Request to send, transmit enable, transmitcharacter length, data terminal readyReceive and Transmit bothfully

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output235Asynchronous ReceiveAn Asynchronous Receive operation begins when the Receive Enable

UM008101-0601 Serial Input/Output236used. If parity is enabled, the parity bit is not stripped from the assembledcharacter for character lengths other

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output237After the Parity Error and Receive Overrun Error flags are latched, the errorstatus

UM008101-0601 Serial Input/Output238character received is loaded into the buffer; the character preceding it islost. When the character that has been

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output239Figure 112. Synchronous FormatsMessage FlowBeginningBeginningBeginning(A) MONOSYNC M

UM008101-0601 Counter/Timer ChannelsA CTC channel may be programmed to request an interrupt every time itsdown-counter reaches a count of zero. Howeve

UM008101-0601 Serial Input/Output240Synchronous Modes Of OperationMonosyncIn a Receive operation, matching a single sync character (8-bit syncmode) wi

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output241Monosync mode, the transmitter transmits from WR6; the receivercompares against WR7.

UM008101-0601 Serial Input/Output242Table6.BisyncTransmitModeFunction Typical Program Steps CommentsRegister Information loadedInitialize WR0 Channel

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output243WR0 Pointer 5 Status affects vector (Channel Bonly). Transmit CRC Enable shouldbe se

UM008101-0601 Serial Input/Output244Synchronous TransmitInitializationThe system program must initialize the transmitter with the followingparameters:

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output245In this phase, there are several combinations of data transfers using inter-rupts an

UM008101-0601 Serial Input/Output246insertion of sync characters when there is no data to send. CRC is notcalculated on the automatically inserted syn

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output2473. ToforcetheZ80SIOtosendCRC,theCPUissuestheResetTransmit Underrun/EOM Latch command

UM008101-0601 Serial Input/Output248Transmit Transparent ModeTransparent mode (Bisync protocol) operation is made possible by theability to change Tra

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output249All interrupts may be disabled for operation in a Polled mode or to avoidinterrupts

UM008101-0601 Counter/Timer ChannelsAccording to Z80 system convention, all addresses in the interrupt serviceroutine table place their low-order byte

UM008101-0601 Serial Input/Output250tions are detected. The mode is reinitialized with the Enable Interrupt OnNext Receive Character command to allow

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output251before the next character is transferred, CRC is calculated on the transferredcharac

UM008101-0601 Serial Input/Output252CRC character has been loaded to the receive buffer, or 20 times (theprevious 16 plus 3-bit buffer delay and 1-bit

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output253WR0 Pointer 1, Reset External/StatusInterruptWR1 Status Affects Vector, ExternalInte

UM008101-0601 Serial Input/Output254Data Transfer AndStatus MonitoringWhen Interrupt on first characteroccurs, the CPU performs thefollowing:During th

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output255SDLC (HDLC) OPERATIONOverviewThe Z80 SIO allows processing of both High-level Synchr

UM008101-0601 Serial Input/Output256The control field of the SDLC frame is transparent to the Z80 SIO, and itis transferred to the CPU. The Z80 SIO ha

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output257“Synchronous Operation” on page 238 section for more details on theinterrupt modes.A

UM008101-0601 Serial Input/Output258information field may be sent to the Z80 SIO using the Transmit Interruptmode. The Z80 SIO transmits the Frame Che

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output259the Z80 SIO with this mode using the Wait/Ready function. The Z80 SIOtransmits the F

UM008101-0601 Counter/Timer ChannelsFigure 4. CTC Pin ConfigurationFigure 5. Package ConfigurationDaisy-ChainInterruptControlCTCControlfrom CPUCPUData

UM008101-0601 Serial Input/Output260has been completely sent, the Transmit Buffer Empty status bit is set and aninterrupt is generated to indicate to

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output2617. The CPU immediately issues a Send Abort Command WR0 to theZ80 SIO.8. The Z80 SIO

UM008101-0601 Serial Input/Output262In all modes, characters are sent with the least-significant bits first. Thisrequires right justification of data

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output263WR4 Parity Information, SDLCMode, X1 Clock ModeWR0 Pointer 1. Reset External/StatusI

UM008101-0601 Serial Input/Output264Data Transfer andStatusMonitoringWhen Interrupt (Wait Ready)occurs, the CPU performs thefollowing:Flags are transm

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output265SDLC ReceiveInitializationThe system initializes the SDLC Receive mode using polynom

UM008101-0601 Serial Input/Output266Because the control field of the frame is transparent to the Z80 SIO, it istransferred to the CPU as a data charac

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output267Special Receive Condition InterruptsThe Special Receive Condition interrupt is not,

UM008101-0601 Serial Input/Output268SDLC Receive TerminationIf enabled, a special vector is generated when the closing flag is received.This signals t

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output269WR4 Parity information, Sync Mode, SDLCMode, X1 Clock ModeWR0 Pointer 5, Reset Exter

UM008101-0601 Counter/Timer ChannelsFigure 6. 44-Pin Chip Carrier Pin Assignments78910111213141516173938373635343332313029N/CN/C+5VN/CN/CN/CCS1CLK/TRG

UM008101-0601 Serial Input/Output270Idle Mode Execute Halt Instruction or some otherprogramSDLCReceiveModeisfullyinitialized and SIO is waiting for th

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output271When End Of Frame Interrupt occurs, theCPU performsthe following:Detection of End-of

UM008101-0601 Serial Input/Output272PROGRAMMINGOverviewTo program the Z80 SIO, the system program first issues a series ofcommands that initialize the

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output273characteristics of the channels. With the exception of WR0, programmingthe write reg

UM008101-0601 Serial Input/Output274Figure 114. Write Register 0Pointer Bits (D2-D0)Bits D2-D0 are pointer bits that determine which write register th

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output275Command 0 (Null). The Null command has no effect. Normally the nullcommand instructs

UM008101-0601 Serial Input/Output276Command 4 (Enable Interrupt On Next Receive Character). If the InterruptOn First Receive Character mode is selecte

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output277The Reset Transmit CRC Generator command normally initializes the CRCgenerator to 0s

UM008101-0601 Serial Input/Output278detection and termination, or at the beginning of CRC or sync charactertransmission when the Transmit Underrun/EOM

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output279Figure 115. Write Register 1Wait/Ready Function Selection (D7-D5). The Wait and Read

Z80 CPU PeripheralsUser ManualUM008101-0601 Table of ContentsiiiTable of ContentsCounter/Timer ChannelsCTCFeatures ...

UM008101-0601 Counter/Timer ChannelsFigure 7. 44-Pin Quad Flat Pack Pin AssignmentsBit 7–Bit 0System Data Bus (bidirectional, tristate). Thisbusisused

UM008101-0601 Serial Input/Output280data. The Wait function is selected by setting D6 to 0. If this bit is 0, theWAIT/READY output is in the open-drai

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output281IORQ and the corresponding S/A and C/D inputs to the Z80 SIO totransfer data. The RE

UM008101-0601 Serial Input/Output282Figure 116. Write Register 2Write Register 3WR3 (Figure 117) contains receiver logic control bits and parameters.(

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output283Sync Character Load Inhibit (D1)Sync characters preceding the message (leading sync

UM008101-0601 Serial Input/Output284Figure 117. Write Register 3Receiver Bits/Characters 1 and 0 (D7 and D6)Used together, these bits determine the nu

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output285Parity (D0)If this bit is set, an additional bit position is added to transmitted da

UM008101-0601 Serial Input/Output286Sync Modes 0 and 1 (D4 and D5)These bits select various options for character synchronization.Figure 118. Write Re

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output287used for both the receiver and transmitter. The system clock in all modesmust be set

UM008101-0601 Serial Input/Output288Request To Send (D1)This is the control bit for The RTSpin. When the RTS bit is set, the RTSpin goes Low; when res

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output289Figure 119. Write Register 5Transmit Bits/Characters 0 and 1 (D5 and D6)Together, D6

UM008101-0601 Counter/Timer ChannelsCEChip Enable (input, active Low). A Low level on this pin enables theCTC to accept control words, interrupt vecto

UM008101-0601 Serial Input/Output290Data Terminal Ready (D7)This is the control bit for the DTR pin. When set, DTR is active (Low);when reset, DTR is

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output291Write Register 7This register is programmed to contain the receive sync character in

UM008101-0601 Serial Input/Output292Read RegistersThe Z80 SIO contains three registers, RR2-RR0 (Figure 122 throughFigure 124), that are read to obtai

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output293Interrupt Pending (D1)AnyinterruptingconditionintheZ80SIOcausesthisbittoset;however,

UM008101-0601 Serial Input/Output294this bit and sets the External/Status interrupt. When the External/Statusinterrupt is set by the change in state o

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output295When the SYNC input goes High again, another External/ Status interruptis generated

UM008101-0601 Serial Input/Output296Clear To Send, (D5). This bit is similar to the DCD bit, except that it showsthe inverted state of the CTS pin.Tra

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output297Read Register 1This register contains the Special Receive condition status bits and

UM008101-0601 Serial Input/Output298I-Field bits are always right justified.If a receive character length is different from eight bits is used for the

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output299Figure 123. Read Register 1Parity Error (D4)When parity is enabled, this bit is set

UM008101-0601 Counter/Timer ChannelsIORQInput/Output Request from CPU (input, active Low). The IORQsignalis used in conjunction with the CE and RD sig

UM008101-0601 Serial Input/Output300CRC/Framing Error (D6)If a Framing Error occurs (asynchronous modes), this bit is set (and notlatched) for the rec

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output301Figure 124. Read Register 2 (Channel B Only)APPLICATIONSOverviewFlexibility and vers

UM008101-0601 Serial Input/Output302Figure 125. Synchronous/Asynchronous Processor-to-ProcessorCommunication (Direct Wire to Remote Locations)Figure 1

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output303The Z80 DMA controller circuit is used with Z80 SIO/2 to transmit thereformatted dat

UM008101-0601 Serial Input/Output304Figure 127. Data ConcentratorKeyboardDisplay/LinePrinterZ80Te r m i na lBusTerminal InterfacesTo R e m o t eHigh-S

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output305TIMINGRead CycleThe timing signals that are generated by a Z80 CPU input instruction

UM008101-0601 Serial Input/Output306Figure 129. Write Cycle TimingInterrupt Acknowledge CycleAfter receiving an Interrupt Request signal, INT pulled L

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output307Figure 130. Interrupt Acknowledge Cycle TimingReturn From Interrupt CycleNormally, t

UM008101-0601 Serial Input/Output308The Tipple time of the interrupt daisy-chain, both the High-to-Low andthe Low-to-High transitions, limits the numb

Z80 CPU PeripheralsUser ManualUM008101-0601 Serial Input/Output309executed or a RETI command is written to the Z80 SIO, resetting theinterrupt-under-s

UM008101-0601 Counter/Timer Channelsan interrupt from any CTC channel. Therefore, this signal blocks lower-priority devices from interrupting while a

UM008101-0601 Serial Input/Output310

UM008101-0601 Counter/Timer ChannelsCTC OPERATING MODESOverviewAt power-on, the Z80 CTC state is undefined. Asserting RESET puts theCTC in a known sta

UM008101-0601 Counter/Timer Channelsused in applications where this output pulse is not required. Additionally, ifthe channel is pre-programmed by bit

UM008101-0601 Counter/Timer ChannelsTiming may be initialized automatically or with a triggering edge at thechannel’s Timer Trigger (CLK/TRG) input. T

UM008101-0601 Counter/Timer Channelsautomatic features in the interrupt control logic, one pre-programmedinterrupt vector suffices for all four channe

UM008101-0601 Counter/Timer ChannelsBit 7 = 1. Each channel is enabled to generate an interrupt request sequencewhen the down-counter reaches a zero-c

UM008101-0601 Counter/Timer Channelswhere tcis the period of System clock, P is the prescaler factor of 16 or 256,and TC is the time constant data wor

Z80 CPU PeripheralsUser ManualUM008101-0601 Table of ContentsivDirect Memory AccessDMAOverview ...33CPUDataTrans

UM008101-0601 Counter/Timer ChannelsLoading The Time Constant RegisterA Time Constant Data Word is written to the Time Constant register by theCPU. Th

UM008101-0601 Counter/Timer ChannelsFigure 8. Mode 2 Interrupt OperationTable 7. Interrupt Vector Register76543210Supplied by User Channel Identifier

UM008101-0601 Counter/Timer ChannelsCTC TIMINGOverviewThis section describes the timing relationships of the relevant CTC pins forthe following types

UM008101-0601 Counter/Timer ChannelsFigure 9. CTC Write CycleCTC Read CycleFigure 10 illustrates the timing associated with the CTC Read cycle. Thisse

UM008101-0601 Counter/Timer ChannelsFigure 10. CTC Read CycleCTC Counting and TimingFigure 11 illustrates the timing diagram for the CTC Counting and

UM008101-0601 Counter/Timer Channelsdetected asynchronously and must have a minimum width. The timingfunction is initiated in synchronization with Φ.

UM008101-0601 Counter/Timer ChannelsThe CTC’s interrupt control logic ensures that it acts in accordance withZ80 system interrupt protocol for nested

UM008101-0601 Counter/Timer ChannelsFigure 12. Interrupt Acknowledge CycleReturn from Interrupt CycleFigure 13 illustrates the timing associated with

UM008101-0601 Counter/Timer ChannelsFigure 13. Return from Interrupt CycleDaisy-Chain Interrupt ServicingFigure 14 illustrates a typical nested interr

UM008101-0601 Counter/Timer ChannelsFigure 14. Daisy-Chain Interrupt ServicingIEI IEOHI+IEIIEOHI+IEIIEOHI+IEIIEOHI+IEIIEOHIIEI IEOHIIEI IEOHIIEIIEOHII

Z80 CPU PeripheralsUser ManualTable of Contents UM008101-0601vDirect Memory Access (continued)WriteRegister3Group...97Wr

UM008101-0601 Counter/Timer Channels

UM008101-0601 Direct Memory AccessDirect Memory AccessDMA OVERVIEWDirect Memory Access (DMA) and DMA Controllers are dedicated tocontrolling high-spee

UM008101-0601 Direct Memory AccessFigure 15. Typical CPU I/O SequenceThe Z80 and Z8000 CPUs both have block-transfer and string-searchinstructions tha

UM008101-0601 Direct Memory Access•The I/O device interrupts the CPU and the block transfer instructionis executed in the CPU interrupt service routin

UM008101-0601 Direct Memory AccessDMACs are used when one or more of the following situations or require-ments are present:•CPU has too much I/O and c

UM008101-0601 Direct Memory AccessDMA CharacteristicsAll DMACs are programmable because the CPU must at least write ablock length (byte count) and sta

UM008101-0601 Direct Memory AccessTransfer MethodsFigure 16 compares conventional CPU instructions and the Z80 and Z8000CPU block transfer instruction

UM008101-0601 Direct Memory Accessalso requires external logic and inhibits memory refresh. Additionally, itreduces DMA throughput.All DMA transfers i

UM008101-0601 Direct Memory AccessModes of OperationWithin each of the methods illustrated in Figure 16c and Figure 16d thereare up to three modes of

UM008101-0601 Direct Memory AccessBus ControlMost DMACs do not control the system bus in the same way that a CPUcontrols it. For example, many DMACs d

Z80 CPU PeripheralsUser ManualUM008101-0601 Table of ContentsviParallel Input/Output (continued)Timing...

UM008101-0601 Direct Memory AccessFor example, the Z80 DMA can be programmed either to stop, interrupt theCPU, continue, or repeat a transfer when a t

UM008101-0601 Direct Memory AccessDMA FUNCTIONAL DESCRIPTIONFeatures•Single Highly Versatile Channel•Dual Port Address Generation with Incrementing, D

UM008101-0601 Direct Memory Access•Programmable Force Ready Condition•Programmable Active State for Ready Line•Programmable DMA Enable•Complete System

UM008101-0601 Direct Memory Accessread and write cycles can be programmed for different timing requirements.If multiple channels are needed, multiple

UM008101-0601 Direct Memory AccessClasses of OperationThe Z80 DMA has three basic classes of operation, and two of the classesare each broken into sub

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UM008101-0601 Direct Memory AccessFigure 19. Basic Functions of the Z80 DMAModes of OperationWithin any class of operation, the Z80 DMA can be program

UM008101-0601 Direct Memory Accessport’s Ready line goes inactive before this occurs, the DMA pauses untilthe Ready line comes active again. This is a

UM008101-0601 Direct Memory AccessFigure 20. Transfer/Search One ByteByteMatch?Write Datato Destination PortIncrement/DecrementDestination Port Addres

Z80 CPU PeripheralsUser ManualTable of Contents UM008101-0601viiSynchronous Modes Of Operation ...240Serial Input/Output (continue

UM008101-0601 Direct Memory AccessFigure 21. Byte ModeRDYActive?Transfer/Search One Byte(SeeFigure 20)• Interrupt• Release Bus• Auto RestartRequest Bu

UM008101-0601 Direct Memory AccessFigure 22. Burst ModeIn the Burst mode (Figure 22), the bus is requested in the same manner aspreviously, but when t

UM008101-0601 Direct Memory Accessattains the bus, the transfers are made at maximum speed. If the transfersare long, however, this mode can interfere

UM008101-0601 Direct Memory AccessFigure 23. Continuous ModeYESRDYActive?• Interrupt• Release Bus•AutoRestartRequest BusEnableDMAEnd?of BlockNONOYESSe

UM008101-0601 Direct Memory AccessTransfer SpeedThe Z80 DMA has one of the fastest maximum transfer rates of any 8-bitDMAC device. This rate is achiev

UM008101-0601 Direct Memory AccessAddress GenerationTwo 26-bit addresses are generated by the DMA for every transfer oper-ation: one address for the s

UM008101-0601 Direct Memory AccessVariable addresses can either increment or decrement automatically fromthe programmed starting address. Fixed addres

UM008101-0601 Direct Memory AccessThe match byte written into the DMA is masked with another byte so thatonly certain bits within the match byte can b

UM008101-0601 Direct Memory AccessAuto RestartBlock transfers can be repeated automatically by the DMA. This functioncauses the byte counter to be cle

UM008101-0601 Direct Memory Accessbe independently programmed as 2, 3, or 4 clock cycles long (more if Waitcycles are used), thereby increasing or dec

Z80 CPU PeripheralsUser ManualUM008101-0601 Table of Contentsviii

UM008101-0601 Direct Memory AccessPIN DESCRIPTIONThe following pin descriptions detail the function of the Z80 DMA externalpins as illustrated in Figu

UM008101-0601 Direct Memory AccessBAIBus Acknowledge In (input, active Low). Signals that the system buseshave been released for DMA control.BAOBus Ac

UM008101-0601 Direct Memory Accessstates to be inserted in the DMA’s operation cycles, thereby slowing theDMA to a speed that matches the memory or I/

UM008101-0601 Direct Memory Accessbe preempted by higher priority devices before the lower priority devicehas been fully serviced.INT/PULSEInterrupt R

UM008101-0601 Direct Memory Accesswhen M1 occurs without an active RD or IORQ for at least two clockcycles, the internal reset is activated at the fal

UM008101-0601 Direct Memory Accesssystem buses, it indicates a DMA-controlled write to a memory orI/O port address.RESETReset (input, active Low) is a

UM008101-0601 Direct Memory AccessFigure 26. 40-Pin DIP Pin AssignmentsZ80 DMA(DIP)

UM008101-0601 Direct Memory AccessFigure 27. 44-Pin PLCC Pin Assignments (Z8410 NMOS)Z8410

UM008101-0601 Direct Memory AccessFigure 28. 44-Pin PLCC Pin Assignments (Z84C10 NMOS)Z84C10

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Z80 CPU PeripheralsUser ManualList of Figures UM008101-0601ixList of FiguresCounter/Timer ChannelsFigure1. CTCBlockDiagram ...

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UM008101-0601 Direct Memory Accesswhich control bytes can be written to the DMA while the CPU has the busbetween byte transfers. This allows the next

UM008101-0601 Direct Memory AccessFigure 30. Write Register Organization (left) and Read Register Organization (right)WRQWR1WR2WR3WR4WR6WR5DataBUS70Ba

UM008101-0601 Direct Memory AccessAddress and Byte CountingAddresses for either port may be fixed at their programmed startingaddress, or they may be

UM008101-0601 Direct Memory AccessNotes:* Address can increment (+) or decrement (-) from the programmed starting address (As), which is the firstaddr

UM008101-0601 Direct Memory AccessNotes:* Address can increment (+) or decrement (-) from the programmed starting address (As), which is the firstaddr

UM008101-0601 Direct Memory AccessWhen the DMA has requested and received the bus from the CPU, otherdevices on the system do not perceive the change.

UM008101-0601 Direct Memory AccessBus Request Daisy-ChainsMultiple DMAs can be linked in a prioritized daisy-chain for the purpose ofrequesting the bu

UM008101-0601 Direct Memory AccessInterruptsConditions and MethodsThe Z80 CPU prioritizes external events in the following order:1. Bus Requests (BUSR

UM008101-0601 Direct Memory Accessstatus bit is not set as it would be without the Auto Restart. Therefore, theinterrupt vector cannot indicate the sp